MEMBER
INVESTMENT PROFESSIONAL
Partner
KEISUKE IDE
- PROFILE
- CAREER
- MEDIA/PUBLICATION
* Keis Ide focuses on deep tech investments in physical science and IT, especially those from academia. He spent 15 years in the US, half of which in Silicon Valley, as an engineer and management consultant.
* He sits on boards of US and Japanese startup companies such as Liminal Insights (US), Nelumbo (US), RICOS (Japan) and Algalbio (Japan).
* He was the lead investor and served as board director at startups such as AI inside (IPO on TSE), GLM Inc. (M&A by HKSE listed company), IID (IPO on TSE), and played an instrumental role for Phyzios' M&A exit to Google Inc.
* He was awarded Forbes Japan Midas List (2017, 2020), Japan Venture Award (2021).
* He sits on boards of US and Japanese startup companies such as Liminal Insights (US), Nelumbo (US), RICOS (Japan) and Algalbio (Japan).
* He was the lead investor and served as board director at startups such as AI inside (IPO on TSE), GLM Inc. (M&A by HKSE listed company), IID (IPO on TSE), and played an instrumental role for Phyzios' M&A exit to Google Inc.
* He was awarded Forbes Japan Midas List (2017, 2020), Japan Venture Award (2021).
He started his career in Silicon Valley as an engineer at KLA in San Jose, CA. He then joined The McKenna Group as a consultant in technology marketing. After returning to Tokyo, he served as a director in a startup company designing ASICs, before joining Globis Capital Partners as a venture capitalist.
He has a BS (Tau Beta Pi) in Systems Engineering from the University of Virginia, and MS Honors in Management Science and Engineering from Stanford University.
He has a BS (Tau Beta Pi) in Systems Engineering from the University of Virginia, and MS Honors in Management Science and Engineering from Stanford University.
C-Based Hardware Design Platform for Dynamically Reconfigurable Processor
publication date 2005
publication description IEEE High Performance Embedded Computing 2005, MIT Lincoln Laboratory
Co-Author and Presenter
Dynamically Reconfigurable Processor Implemented with IPFlex’s DAPDNA Technology
publication date Aug 2004
publication description IEICE Transactions on Information and Systems, August 2004 Vol.E87-D No.8
Co-Author